Tech Blog

LabVIEW RT Project

Overview

This blog gives a very brief introduction to setting up a real-time cRIO project in LabVIEW. This is often the first step required for any control project in LabVIEW, and we will refer to this blog from some of our other blogs.

LabVIEW environment

First things first: you will need a LabVIEW real time license to run real time projects! This includes the LabVIEW real-time module, and we generally also recommend the LabVIEW FPGA module to go along with this. The real time environment enables control loop rates of order 1ms, while the FPGA environment enables control loop rates of order microseconds. Once you have all modules installed, LabVIEW should start up as shown below

The chip-type icon indicates that the FPGA module is installed, and the clock icon represents the real time module.

Setting up a cRIO real time project

Start LabVIEW and open an empty project. There are other option, but generally we feel starting an empty project is the cleanest way to get started. Right click on the My Computer level and add a target as shown

Under the Target and Devices dialog, add the Real-Time CompactRIO (cRIO)

Once you add this target, a pop up will ask you to select the RIO Programming Mode. If you are unsure here, select the Scan Interface mode for beginner type projects. This option can also be changed later on in the project settings.

If you want to try some of the real time loops at this stage, continue with this blog. If you also need FPGA functionality, keep reading here.

Adding the cRIO FPGA

Adding the cRIO FPGA to the LabVIEW project is simple. Right click under the cRIO Chassis and select New > FPGA target option.

You can now add VIs under both the real time target (right click at the NI-CRIO level and select New > VI) and the FPGA target (right click at the FPGA target level and select New > VI). Once these VIs are added, your project should look like this.

To illustrate where the various VIs execute, we have named the cRIO level VI “runs_at_RT.vi” and the FPGA level VI “runs_as_FPGA.vi”.

With the cRIO RT / FPGA targets added, you can test some RT loops as described here. A more advanced application example including both the RT target and the FPGA is described here.